International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2010 : Albany, N.Y.)
Title:
Stress management for 3D ICs using through silicon vias : International Workshop on Stress Management for 3D ICs Using Through Silicon Vias, Albany, NY, U.S.A, March 16, 2010, San Francisco, CA, U.S.A., July 13, 2010, Dresden, Germany, October 20, 2010 / editors, Ehrenfried Zschech ... [et al].
Zschech, Ehrenfried. International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2010 : San Francisco, Calif.) International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2010 : Dresden, Germany)
Notes:
Includes bibliographical references and index.
Contents:
White papers -- Multi-scale modeling -- Multi-scale materials parameters -- Multi-scale stress characterization -- ISV : process characterization and failure analysis.
This resource is supported by the Institute of Museum and Library Services under the provisions of the Library Services and Technology Act as administered by State Library of Iowa.