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01990aam a2200325Ii 4500 001 A54B869A332F11E49E51C4E1DAD10320 003 SILO 005 20140903010030 008 130907s2014 sz a b 001 0 eng d 020 $a 331901112X 020 $a 9783319011127 035 $a (OCoLC)857975666 040 $a BTCTA $b eng $e rda $c BTCTA $d UKMGB $d CDX $d OCLCO $d YDXCP $d OCLCQ $d IXA $d NhCcYBP $d SILO 050 4 $a TK7895.E42 $b J38 2014 082 04 $a 621.4 $b 23 100 1 $a Javaid, Haris, $e author. 245 10 $a Pipelined multiprocessor system-on-chip for multimedia / $c Haris Javaid, Sri Parameswaran. 264 1 $a Cham : $b Springer, $c [2014] 300 $a viii, 169 pages : $b illustrations (some color) ; $c 24 cm 520 $a This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. 504 $a Includes bibliographical references and index. 650 0 $a Systems on a chip. 650 0 $a Multiprocessors. 650 0 $a Pipelining (Electronics) 650 0 $a Multiprogramming (Electronic computers) 650 0 $a Embedded computer systems $x Design and construction. 700 1 $a Parameswaran, Sri, $d 1962- $e author. 941 $a 1 952 $l OVUX522 $d 20191211032037.0 956 $a http://locator.silo.lib.ia.us/search.cgi?index_0=id&term_0=A54B869A332F11E49E51C4E1DAD10320Initiate Another SILO Locator Search